In June 2026, OpenAI released Jalapeño, its in-house inference chip. The headline number was time: from concept to tape-out in just nine months, with OpenAI’s own press release calling it “the fastest chip design ever”.
That naturally invites a tempting inference: AI can now design chips.
But a Business Insider interview with OpenAI co-founder Greg Brockman offers a much more measured account. Brockman explains that the inputs the AI received were components engineers had already optimized; within that framework, the model used large amounts of compute to search for better parameter combinations. The result was significant area reductions and weeks shaved off the schedule. He was careful to add: “I don’t think any of the optimizations that we have are ones that human designers couldn’t have come up with.” The engineering team reviewed the results afterwards and reacted with: “Yeah, this was on my list” — it just happened to be twentieth in the queue, and would have taken at least another month to reach manually.
Those statements pin AI’s actual contribution to a specific scope: optimization search in the back end of physical design. Physical design is one of the most time-consuming stages of chip design — it requires deciding the precise placement of hundreds of millions of transistors on silicon, packing some areas tight and leaving others room, satisfying routing rules while minimizing area. Engineers iterate through this with experience and tools; AI uses compute to brute-force thousands of placements and filters out the few that engineers would have arrived at in the next iteration anyway. The time saved is real, and the compute poured in is substantial (Brockman’s phrase was literally “pour compute into it”). But this activity is a long way from design itself — the gap between a search engine finding a paper and a search engine writing one.
When OpenAI and Broadcom published the official Jalapeño announcement on June 24, 2026, the language had tightened further. The entire text mentions only “using OpenAI models to accelerate parts of the design and optimization process,” with no mention of “nine months” or “fastest ever.” The shift from candor in the interview to restraint in the announcement is itself a tell about the real boundary of AI’s role.
If AI only did optimization search, where did the tight nine-month cycle come from? The answer points mainly at OpenAI’s partner, Broadcom.
Broadcom is the world’s leading ASIC services company. Before Jalapeño, it had already built custom chips for Google’s TPU, Meta, ByteDance, and Microsoft’s Maia, and it holds a mature IP library, off-the-shelf networking silicon (the Tomahawk family), and a stable tape-out pipeline through TSMC. OpenAI did the architecture; Broadcom did the silicon implementation: translating the design into transistor-level physical layout, synthesis, packaging, and tape-out. The labor and experience required for those stages far exceed what architecture itself demands.
A CNBC report from October 2025 disclosed that the two sides described themselves as having “been working together for 18 months.” Add the later-announced nine months, and the actual total span is roughly 21 months. The “nine months” almost certainly refers to the period between RTL freeze and tape-out. RTL is the code describing the chip’s logic; freeze means the design no longer changes, after which it enters pure engineering implementation. In other words, nine months was not the time to draw a chip on a blank sheet — it was the time from design lock to chip out the fab door.
Broadcom’s investor relations press release is honest about this detail: the “we believe to be the fastest” in OpenAI’s version becomes “may be the fastest” in Broadcom’s. A public company unwilling to underwrite a partner’s inflated narrative — that cooling gesture is more persuasive than any external analysis.
At this point the core of OpenAI’s story is clear: AI did post-layout optimization search and saved a few weeks; the tight cycle came mainly from buying twenty years of accumulated engineering experience. But does that mean AI is broadly weak across chip design? Step back, and the answer gets more complicated.
A chip moves from idea to silicon through roughly these stages: architecture design, deciding the chip’s functional and performance targets; writing logic code (RTL) that describes circuit behavior; functional verification, checking that the logic is correct (the most time-consuming stage, often eating more than half the schedule); physical design, turning logic into transistor placement and routing; tape-out, handing the design to the fab; and finally manufacturing itself — lithography, etching, defect inspection. Along this chain, AI’s performance degrades steadily from back end to front end. There is no clean binary of “works” and “doesn’t work.”
The manufacturing end is AI’s most mature territory — and the part least discussed in public. NVIDIA’s cuLitho is the most representative case: 500 DGX H100 GPU servers replace the 40,000 CPU servers previously required for computational lithography, with speedups up to 40x, and it has entered TSMC’s volume production flow. A photolithography mask that used to take two weeks to process can now run overnight. ASML has also committed to integrating GPU acceleration into all of its lithography software.
The other manufacturing-side pillar is defect inspection. Wafer production generates large numbers of defects, and you have to distinguish real defects from noise. Applied Materials’ inspection systems use classical machine learning for this; they currently have more than 1,500 units installed worldwide, covering every advanced-process customer. This is probably the hardest-evidenced, longest-running AI application in the chip supply chain — it just isn’t on the public’s radar.
A distinction worth making here, because it gets conflated. cuLitho’s core is not a new algorithm — it’s moving lithography computation from CPU to GPU, which is hardware acceleration. Defect inspection uses convolutional neural networks for image classification, a technique that has been deep learning’s home turf since 2012. These “most mature” AI applications on the manufacturing side use technologies that matured a decade ago and have nothing to do with the generative AI generation of ChatGPT. What made them deployable at scale today is cheap GPU compute and gradual industry adoption — not an algorithmic breakthrough.
One layer up from manufacturing sits parameter optimization and verification coverage inside EDA tools. EDA — electronic design automation — is essentially CAD software for chip engineers. In this layer, AI has already become a real commercial product. The two EDA giants, Synopsys and Cadence, have each launched reinforcement-learning-driven optimization tools that search enormous design spaces for optimal parameter combinations.
The most reliable gains come from named-customer endorsements: Samsung, using Synopsys’s DSO.ai on its 2nm process, achieved 12% performance improvement, 25% power reduction, and 5% area shrink; MediaTek, using Cadence’s Cerebrus, saw 5% area reduction, 6% lower power, and over 50% productivity improvement. Renesas’s case is more telling: one engineer completed in 10 days what previously required multiple engineers and several months. In verification, Synopsys’s VSO.ai delivered Renesas a 10x reduction in coverage holes and a 30% productivity improvement.
Independent research firm SemiAnalysis provides commercial-side evidence: Cadence Cerebrus grew from 180 tape-out projects to over 1,000 in two years, and all of the global top-ten digital-chip customers have adopted it. But one number here is easy to misread: 100% penetration is adoption rate, not a guarantee of significant improvement on every use. Many customers’ actual experience is “using it, the result is no worse than manual tuning” — not that every run delivers those headline percentage gains. AI is an accelerator here; engineers still define the problem and still make the architectural decisions.
Equally important to separate: the core engines of DSO.ai and Cerebrus are reinforcement learning and Bayesian optimization, not generative AI. RL’s application in EDA began landing around 2020 and became a product standard by 2026. Vendors occasionally slap a “generative AI” label on marketing materials, but what the underlying engine actually does is search a design space for an optimum — not generate content from nothing the way ChatGPT does.
Move further toward the front end, and the picture changes. AlphaChip is the AI-driven chip-design technique Google has pushed since 2020, using reinforcement learning for macro placement of large chip blocks. Google repeatedly emphasizes that it has been used in tape-out across multiple TPU generations, which carries real narrative weight. But in 2025, a team at UC San Diego led by Kahng published a paper in an IEEE computer-aided design journal: they took Google’s own publicly released pretrained model, gave it enough compute to train to convergence, and ran it on public benchmarks. The result: classical simulated annealing still matched or beat the RL method, and did so faster and with fewer resources.
The root cause, as another independent paper — ChiPBench — explains in detail: reinforcement learning optimizes proxy metrics, like approximate wirelength and congestion, but there is a disconnect between those approximations and the chip’s actual final performance. Improving a proxy score does not mean the chip is actually better. “Deployed in production” and “scientifically superior” are two different things. Google has real tape-out records, but in every public, controlled comparison, RL has not beaten classical methods.
The technologies used at those first three locations — GPU acceleration, CNNs, RL search — all predate 2022. It is only when you get to using large language models to directly generate chip logic code that you actually enter the territory of generative AI. And it is precisely here that AI’s performance drops sharply. NVIDIA’s research lead Mark Ren, in a 2025 talk, offered a stark contrast: on the public VerilogEval benchmark, AI’s pass rate reaches above 70%, but switch to CVDP, a benchmark closer to real production scenarios, and the pass rate collapses to between 10% and 40%. On the hardest category, RealBench, no AI system has yet solved a single problem.
An even more surprising data point comes from NVIDIA itself. Their in-house domain model, ChipNeMo, purpose-built for chip design, scores 43.4% on RTL generation — worse than the general-purpose GPT-4 at 60%. ChipNeMo’s actual role in real engineering is answering engineers’ questions, generating automation scripts, and summarizing bugs — not replacing engineers writing logic code. A 95% pass rate on VerilogEval sounds like AI can now write chip code, but those problems are all under 100 lines, single small modules. Real chip design is a multi-billion-transistor, multi-team, two-year system-engineering effort.
Lay those four locations side by side and a gradient emerges on its own. cuLitho and defect inspection on the manufacturing end are the most mature; EDA optimization has become a commercial product; AlphaChip is contested; LLM-based RTL generation is still in the lab. This gradient has nothing to do with company, model, or marketing budget — it points to something more fundamental: different stages offer AI very different learning conditions.
The manufacturing end matured first because the feedback it gives AI is fast and accurate. Every wafer produced is a labeled sample; metrology equipment tells you on the spot whether line widths are right and where defects sit. The design end is the opposite: whether a tape-out is right or wrong is not known until the chip comes back months later, and every step in between lacks real feedback. Target shape differs too. Yield, defect density, line width are continuously measurable physical quantities, and optimizing them maps directly onto business value. But how a chip’s architecture should be designed is hard to write down as a function — it is all implicit trade-offs encoded in experience. Cost of verifying output also favors manufacturing: change a lithography parameter and the wafer prints and you measure it; classify a defect and an electron-microscope image settles it. Many design-side decisions have no such ground-truth measurement and can only be judged through simulation, which itself diverges from reality.
The cost of being wrong is not in the same order of magnitude either. Misclassify a defect on the manufacturing line and you re-inspect; in the worst case you scrap one wafer — thousands to tens of thousands of dollars, with redundant safeguards on the process line. A design-side error can scrap an entire tape-out batch, with losses routinely in the millions of dollars plus months of cycle time for a re-spin. The shape of the problem is equally lopsided: defect inspection is image classification, computational lithography is numerical optimization plus physics simulation — CNNs and classical optimization have been grinding on these for over a decade. RTL generation is open-domain generation that requires understanding specs, reasoning across modules, and maintaining global consistency — areas where LLMs are still far from crossing the production threshold.
Manufacturing wins on all five dimensions, so AI there has long been invisible infrastructure — never making headlines, earning money every day. RTL generation wins on almost none, so it is still stuck at the benchmark stage. In the middle, EDA parameter optimization and verification closure win on two or three: quantifiable targets, massively parallel experimentation, simulation-verifiable outputs. That is why they became commercial products — but still accelerators.
There is one more easily overlooked layer. Every stage above that already works uses technology that matured before 2022. GPU parallel computing, CNNs, RL search — their mathematical foundations and engineering practices were polished long ago. The technology that genuinely belongs to this AI wave — large language models — only shows up at the very front end, on the hardest tasks, exactly where it still cannot perform. In other words, “what AI can do in chip design” and “what is new in AI” barely overlap: what works could be done a decade ago, and what is new still cannot be done well. Whether AI is useful in a domain depends not only on how friendly the learning environment is — it also depends on which generation of “AI” you are actually talking about.
Step outside chip design and bring this logic back to your own domain, and it becomes a judgment tool. Faced with any “AI can now do X” headline, first look at feedback speed: is the right-or-wrong answer known in seconds or minutes, or does it take months or years to verify? Then look at target shape: is it a clean number you can write down, or a tangle of interdependent, hard-to-quantify engineering trade-offs? Finally, look at verification cost: is checking the output cheap, or does it require expert review every time?
There is another question that is easy to skip: what specific technology does the “AI” in the headline refer to? If it is GPU acceleration, classical machine learning, or RL search, it has been capable for a decade — today’s deployment rides on cheaper compute and gradual industry adoption, not an algorithmic breakthrough. If it is an LLM or generative AI, you additionally have to ask whether it has crossed the threshold from benchmark to production. Many “AI disrupts industry X” stories package the maturity of the former as the breakthrough of the latter.
Fast feedback, clear targets, cheap verification, and mature technology — in domains with all four, AI is probably already making money there, just not in the headlines. cuLitho and defect inspection are examples: absent from public discussion, generating real economic returns every day. Slow feedback, fuzzy targets, expensive verification, and dependence on the latest GenAI — in domains like that, AI is probably still stuck benchmark-chasing: loud headlines, unusable in production. LLMs generating chip code is the canonical case.
Back to the story this article opened with. OpenAI’s Jalapeño lands squarely on every dimension of this framework. AI’s real value sits inside the friendly learning environment of physical-design optimization, where it saved a few weeks. But OpenAI packaged it as “AI designed the chip,” because that is a better headline. Understanding the gap between those two statements is more useful than chasing any single “AI disrupts industry X” story.