On May 14, 2026, Cerebras debuted on the Nasdaq. Following the opening bell, its share price climbed steadily, closing up 68% on its first day and pushing its intraday valuation near $100 billion. Chinese tech media was immediately flooded with coverage. On the Xueqiu community, an analysis post described it as an ASIC (application-specific integrated circuit) designed from scratch specifically for modern large language model inference. A report by TMTPost (syndicated on platforms like Sina Finance) noted that its chip integrates approximately 4 trillion transistors and 900,000 dedicated AI compute cores. More than two years earlier, an article published by Xinhua Net used the relatively neutral phrasing of “900,000 AI cores.” With just the one-word shift from “AI cores” to “dedicated AI cores,” public perception of the company quickly solidified: this is a domain-specific chipmaker that bakes specific AI algorithms directly into silicon.
I initially fell into the same intuitive classification trap myself, assuming it was nothing more than a giant ASIC that turns neural networks into ultra-large-area wafer-scale circuits. But following the chip’s underlying architectural logic, the reality is quite the opposite. The criterion for whether a chip is an ASIC has never been whether fixed physical structures exist on the silicon—because no chip in the world exists without fixed circuitry. The instruction set architecture, integer and floating-point units, and multi-level cache hierarchies of an x86 CPU are all built into silicon, yet no one has ever classified a CPU as an ASIC.
The true dividing line lies in which abstraction layer is frozen at the moment the chip leaves the factory. If leaving the factory freezes only the machine’s baseline capabilities—which instructions it supports, how cores interconnect, and where memory is distributed—while leaving the specific programs to be loaded via software post-manufacture, that is a general-purpose processor. If leaving the factory freezes the algorithm itself into the circuitry, making the hardware synonymous with the algorithm, only then is it an ASIC. Take a Bitcoin mining rig as an example: it is not running the SHA-256 hashing algorithm; its entire block of custom circuitry is the SHA-256 algorithm.
Apply this frozen-layer test to Cerebras’s Wafer-Scale Engine (WSE): what is frozen upon leaving the factory are 900,000 general-purpose processor cores, 44GB of on-chip SRAM, an on-chip network interconnecting all cores, and a general-purpose instruction set. As Cerebras’s official architecture documentation states: the foundation of each compute core is a fully programmable processor that supports arithmetic, logic, load and store, compare, and branch instructions just like a general-purpose processor. This silicon understands addition, subtraction, multiplication, and division, and knows how to communicate with neighboring cores, but it has no concept of a transformer. Between the model and the wafer sits a compiler: run Llama today, and the compiler maps Llama’s computational graph across these 900,000 cores; switch to a new network architecture tomorrow, simply recompile, and the same wafer runs it without skipping a beat.
There is an even more counterintuitive fact: when running large language models, parameter weights do not even reside permanently on the wafer. WSE’s 44GB of on-chip memory cannot hold modern model parameters that routinely scale to hundreds of gigabytes. Instead, Cerebras adopts a weight streaming approach: weights are stored in external memory and streamed through the wafer layer by layer during inference, discarded immediately after use. 36Kr pointed out this detail in a report: in Cerebras’s architecture, model weights are never stored in SRAM. Thus, the popular notion of “etching neural networks onto a wafer” falls apart on two levels: what is frozen on the silicon is not a neural network, and the neural network’s weights do not permanently reside on the wafer at all.
The phrase “hard-etched into the chip” cited in media reports isn’t inherently wrong—it just targets the wrong subject. The startup that genuinely hardcodes model weights into silicon is Taalas. Using a Mask ROM process, they hardcode model weights into the metal interconnect layers so that a chip can only ever run inference on one specific model from the day it is fabricated; the company was acquired by AMD in August 2026. Stepping one tier closer toward general-purpose computing is Etched, whose Sohu chip is dedicated exclusively to the transformer architecture—CEO Gavin Uberti publicly acknowledged that if transformers fall out of favor, the company fails. MIT Technology Review’s assessment of Taalas’s path noted that the chip is completely non-programmable, leaving essentially zero margin for error.
Arrange these hardware approaches along a single axis named “which layer is frozen upon leaving the factory”: - General-purpose CPUs freeze the basic instruction set; any compliant program can run on them. - TPUs and Cerebras’s WSE step one level further: the entire machine is built specifically for tensor computing workloads, with compute cores, local memory, and interconnect topologies deeply tailored around matrix operations, but the final computation to be executed remains entirely determined by software. - Etched freezes the algorithm itself into hardware, meaning the entire chip can only process transformer structures. - Taalas takes it even further by freezing specific weights into the metal layer, binding a chip to a single model for its entire lifetime.
This is a categorization framework that offers real discriminative power. Putting Cerebras and Taalas into the same drawer labeled “dedicated chips” is no different from categorizing both lions and penguins as non-flying animals—technically unassailable on paper, but the taxonomy loses all analytical utility.
Of course, WSE is certainly not a general-purpose computing platform like a CPU. Its core microarchitecture and low-level toolchain are deeply customized for tensor workloads, placing it alongside TPUs in the domain-specific category. However, it remains two entire layers away from freezing concrete computations. If targeted optimization for AI workloads is all it takes to qualify as an ASIC, then GPUs equipped with Tensor Cores would also be ASICs, and TPUs would be ASICs, rendering the concept of a dedicated chip entirely incapable of describing any distinct technical characteristic.
Beyond the frozen layer at fabrication, there exists a second, orthogonal dimension: scale. Traditional chip manufacturing photolithographs hundreds of small dies onto a single wafer, dicing and packaging them before linking thousands of individual chips into a distributed cluster via external networking; the intermediate form integrates multiple bare dies onto a single substrate using advanced packaging. Cerebras stands at the extreme right end of the scale axis: the entire 46,225 mm² wafer undergoes zero physical dicing—offering an area 57x that of Nvidia’s H100—and is delivered directly as a single massive chip. On the frozen-layer spectrum, it sits almost on the same side as GPUs; its core wager is placed entirely on the scale axis. Today’s inference chip landscape spans across both axes: Nvidia links thousands of discrete chips into compute backbones via high-speed networking, Groq bakes deterministic execution into hardware, OpenAI chooses in-house inference ASICs, and only Cerebras wagers on the far right end of the scale axis. This is the crucial coordinate system for understanding this company, and all subsequent engineering implementations and commercial maneuvers unfold along these two axes.
Given that it is fundamentally an array of general-purpose processor cores, where does its confidence to challenge Nvidia in inference workloads actually come from? The answer lies in the computational characteristics of large language model inference. LLM text generation is a strictly serial autoregressive process: the second token can only be computed after generating the first; the third token can only be derived once the first two exist. During this decode phase, generating each individual token requires the system to read the entire set of model weights from start to finish. At this point, the powerful floating-point compute units on a GPU often sit starved and waiting; the throughput bottleneck of the entire system gets trapped by the speed of shuttling weights from video memory to compute cores—what the semiconductor industry commonly refers to as the memory wall.
Taking Nvidia’s Blackwell architecture B200 as an example, its equipped HBM memory bandwidth reaches 8TB/s. Even at this throughput, reading through 16GB of FP16 weights in full takes about 2 milliseconds, capping a single card’s output at a few hundred tokens per second at most. The bottleneck slowing down generation speed has never been multiplication compute capacity; the real overhead lies entirely in long-distance data movement.
Cerebras’s solution is to build memory directly into the compute array itself. 44GB of on-chip SRAM is distributed across 900,000 cores, with each core flanked by its own dedicated high-speed storage. The physical distance between the two is merely tens of micrometers, and data reads require only a single clock cycle. The on-chip memory bandwidth across the entire wafer reaches 21PB/s—thousands of times greater than the H100’s memory bandwidth. According to official figures, Cerebras achieves an average inference speed exceeding 2000 tokens/s, whereas traditional GPU solutions typically hover between 200 and 300.
This also explains why Cerebras’s commercial narrative exploded after 2024. Model training is a highly parallelizable task where massive amounts of data can be partitioned into batches and distributed across tens of thousands of GPUs for simultaneous computation—GPU’s natural home turf. In contrast, the decode phase of inference is a purely serial chain where every token depends on the previous step’s output, placing the throughput bottleneck squarely on weight retrieval speed, precisely matching the core strength of wafer-scale on-chip bandwidth. Founded during the training era, the company waited ten years until the industry’s primary bottleneck finally shifted to its greatest strength. As CEO Andrew Feldman put it: the deciding factor in inference is memory bandwidth, and putting compute and memory on the same piece of silicon was the bet they placed from day one.
To truly integrate compute and memory onto the same piece of silicon means eliminating the long-distance data pathways found in traditional GPU clusters. In conventional cluster architectures, data must shuttle back and forth between compute cores and HBM, between GPUs, and even across server racks. Nvidia has pushed external interconnect bandwidth to the limit with technologies like NVLink and InfiniBand, but physical distances within datacenters remain unavoidable. Cerebras’s vision is to completely fold these macroscopic distances into a single microscopic wafer. Communications that previously had to traverse chip pins, circuit boards, and switch fiber cables are all collapsed within the same slice of silicon, compressing the interconnect distance of an entire distributed cluster down to tens of micrometers.
On the software side, this folding provides an exhaustive reduction in overhead. Training or deploying large models across traditional GPU clusters requires engineers to meticulously partition model parameters into shards distributed across individual GPUs, managing tensor parallelism, pipeline parallelism, gradient synchronization, and node failure recovery—all backed by a massive, complex distributed software stack to maintain orchestration. On the WSE, however, compilers and higher-level software always see a single contiguous block of high-capacity memory alongside hundreds of thousands of general-purpose processor cores, dissolving the complex engineering overhead of model parallelism directly at the underlying hardware layer.
This bet was placed in late 2015. The five founding members had previously worked together at microserver company SeaMicro; after its acquisition by AMD, they set the new venture’s goal at a symbolic height: to earn a place in the Computer History Museum. According to SV 101’s interview with early investors, a pitch slide Andrew Feldman used for fundraising listed seven core bottlenecks in deep learning, all pointing to a single conclusion: training took too long. At the time, transformers had not yet emerged, and today’s LLM wave was nowhere on the horizon. The team’s wager had nothing to do with specific model algorithms, but rested on a deeper conviction: artificial intelligence would evolve into an unprecedented computing workload, demanding a computer designed for it from the physical foundation up. This insight predated transformers by nearly two years, but the vision of keeping an entire wafer uncut pushed the bet straight to the cliff edge of semiconductor manufacturing laws.
In the history of semiconductor manufacturing, wafer-scale integration has been a 70-year engineering graveyard. Pioneer companies like Trilogy took on whole-wafer manufacturing, only to eventually succumb to yield issues.
The root of the impasse can be directly calculated via defect density. TSMC’s 5nm process has a defect density of approximately 0.001 per mm²; across the 46,225 mm² of the WSE-3, every wafer inherently carries around 46 defects. Traditional chip design cannot tolerate this number: if a defect lands on core circuitry, the entire chip is scrapped, rendering the yield of a wafer-scale chip probabilistically close to zero. Larger surface area yields more defects, and larger chips mean single defects inflict greater damage—worsening the problem from both ends.
Cerebras’s breakthrough began with shrinking the failure unit. A single SM core on an H100 measures roughly 6 mm², where a defect hit destroys the entire unit; WSE reduces core size to 0.05 mm²—about one percent of the former—slashing the impact area of the same defect by roughly a hundredfold. On top of that, redundancy is layered in: the wafer is provisioned with an extra 1% to 1.5% of spare cores. Once factory testing flags defective nodes, the on-chip network reroutes around them at the hardware level, redirecting compute flows to healthy cores. With an expected 46 defects against 9,000 to over 13,000 spare cores, a 200-to-300-fold redundancy margin stands between the two figures. What software sees is always a logically complete chip.
The concept of redundancy itself has precedent. Beyond its 132 active SMs, the H100 fabricates 12 extra SMs for fault tolerance, and memory manufacturers have used spare cells to repair defects for decades. Cerebras’s innovation lies in scaling this mechanism to the dimension of an entire wafer, thereby reframing the yield question: rather than asking for the probability of zero defects across the entire wafer—a figure that decays exponentially with area—ask instead for the probability that the total defect count exceeds the spare budget. Across a statistical base of hundreds of thousands of cores, the Law of Large Numbers turns around to safeguard yield.
Here lies the hardest evidence for the opening premise: the reason damaged cores can be dynamically isolated by hardware and compute tasks smoothly remapped is precisely because the computation process is dynamically dispatched by a software compiler rather than hardwired into specific silicon circuits. If the algorithm itself were hardware circuitry, a damaged core would mean the permanent loss of an irreplaceable function, leaving the system with no way to reroute. Full-wafer dynamic fault tolerance and programmability are essentially two sides of the same coin: the ability to freely bypass bad cores is proof that the program was never frozen in silicon.
Beyond the wafer lies another suite of physical engineering designed from scratch. Dissipating approximately 25kW of power on a dinner-plate-sized piece of silicon produces a power density far exceeding conventional chip thermal paradigms, with no off-the-shelf solutions for power delivery, liquid cooling, or rack interfaces. According to SV 101’s interview with early evaluator Greg Diamos, when he first visited Cerebras’s office, engineers first showed him a heatsink customized for this wafer. His immediate reaction was that graphics cards didn’t need anything like that—until they brought out the complete, uncut wafer. In the coordinates of this article, that moment of divergence landed precisely on the scale axis: what was being built here belonged to a completely different order of magnitude than merely a better graphics card.
While engineering had to absorb the extreme scale of manufacturing, the people outside the semiconductor industry who dared to pay for this extreme dimension back then were armed with empirical data from frontier research. In late 2015, before transformers had appeared, a significant part of why external researchers firmly believed in a future compute deficit came from Baidu SVAIL (the following account is based on SV 101’s reporting). Andrew Ng’s team was running training experiments with large-scale language models at the time, deriving the Scaling Law: larger models, more data, and greater compute yield better and predictably scaling performance. Team member Dario Amodei later brought this insight to OpenAI. Extrapolating along this empirical curve, LLMs hitting a compute ceiling was only a matter of time. Starting in 2016, SVAIL searched globally for compute alternatives beyond Nvidia and found Cerebras—which didn’t even have a product yet. This bet was not reckless hype at the time, but a rational extrapolation of experimental data; the wager was that workloads would continue to grow, rather than on any specific architecture. This also explains why it stands so close to GPUs on the frozen-layer spectrum: a company betting on workload scale has no reason to weld its architecture shut.
The workload bet paid off, and its usage ten years later validates this coordinate system. The March 2026 collaboration between AWS and Cerebras is a direct embodiment of the two-stage nature of inference: prefill processes prompts in parallel and is handed to AWS’s proprietary Trainium; decode generates tokens one by one in strict serial fashion, playing directly to the strength of wafer-scale bandwidth. No single architecture dominates the entire inference workload, and in this partnership, Cerebras takes on the decode half. Andrew Feldman took this position to the fullest in public statements: partnering with all hyperscalers, with Nvidia being the sole omission from the list.
The counter-example arrived three months later. OpenAI and Broadcom jointly announced their first in-house inference chip, Jalapeño—a true language model inference ASIC with dedicated circuitry frozen down to the algorithm tier. The intriguing part is that OpenAI is buying both sides: placing wafer compute orders on the scale of $20 billion with Cerebras on one end, while developing in-house ASICs to hardware-harden inference logic on the other. This neatly lays out the coordinate system from the beginning of this article across the market: true ASICs and programmable wafers stake out opposite ends of the spectrum, and the market is paying for both positions simultaneously.
The market’s willingness to fund divergent approaches simultaneously provides a clear footnote to this computing quest that began a decade ago. As early as 2022, the Computer History Museum established a permanent exhibit for WSE-2 titled The Biggest Chip in the World. The mark the five founders sought to leave in 2015 materialized in this manner, in a form far more concrete than they had originally imagined. A decade later, this concept has reached the stage of being tested quarter by quarter by capital markets, and understanding what it is truly betting on is the prerequisite for anticipating where this test leads.
The next time you see the “dedicated chip” label slapped onto it, return to that more accurate technical coordinate: what it freezes upon leaving the factory is the machine itself, leaving the programs to software. The only thing solidified onto the silicon is a single engineering conviction: data should never have to travel across long-distance cables.